Day 24
I. Last Time:
Lab #3 Due!!!
Hw #6 Posted Today (Short / Easy)
Lab #4 Posted Today (~ length of lab #2+)
A. Boolean Logic/Algebra -
Equations to describe binary machine.
May want to simplify / manipulate
B. Gates: AND, OR, NOT
Engineers found early on that things called gates could be
made from relays/transistors. These gates are physical
implementations of the logic operations:
AND Gate:
OR Gate:
NOT Gate:
XOR Gate:
Others: NOR, NAND, etc.
Since these are physical systems, they have a physical arrangement
which creates specific orders of operations.
Ex: A*(B+C)
Moreover, these gates have a property called propagation delay.
This "delay" is the time it takes a change to travel through
the gate.
Gates are "mechanical" devices it takes time for information
to travel through them. This time is called propagation delay
and is one of the most important factors in desiging computers
and esp. high speed digital systems.
The maximum clock speed is often dependent on this propagation delay.
II. New Stuff
A. Different Equation Styles: SOP vs. POS
SOP - Sum of Products: A*C+B*C+A*D+B*D
POS - Product of Sums: (A+B)*(C+D)
Truth Table
A B C D AC BC AD BD AC+BC+AD+BD A+B C+D (A+B)*(C+D)
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 0 0 1 0
0 0 1 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 0 1 0 0
0 1 0 1 0 0 0 1 1 1 1 1
0 1 1 0 0 1 0 0 1 1 1 1
0 1 1 1 0 1 0 1 1 1 1 1
1 0 0 0 0 0 0 0 0 1 0 0
1 0 0 1 0 0 1 0 1 1 1 1
1 0 1 0 1 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 1 1 1 1
1 1 0 0 0 0 0 0 0 1 0 0
1 1 0 1 0 0 1 1 1 1 1 1
1 1 1 0 1 0 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
A*C+B*C+A*D+B*D == (A+B)*(C+D)
Conclusion: There are multiple "correct" ways to write a
logic equation. We will be using the SOP form
most because it's the "easiest" to read.
A*C+B*C+A*D+B*D:
We just look at each "term". We know that
then we see ones in A and C the whole eq.
will be true.
NOTE: That the "table" is just created by counting through
the binary numbers using the "inputs"
Boole found that these simple operations could be combined with
statements to answer questions:
Now Let's look at a simple equation:
A+B*C*/D
When is this equation true? Well, one way to find out is to
create a truth table:
1) If N variables, 2^N values in the truth table (Binary!)
2) Solve smaller parts of the truth table
You can also take a known truth table and generate an equation from
it. We'll make a SOP (Sum-Of-Products) equation first:
Look at Page B-5.
Let's look at equation F:
When is F true? When a=1,b=b,c=1. I.e. A*B*C
What about an equation for E:
/A*B*C+A*/B*C+A*B*/C
Notice that we:
1) Create a specific 1
2) Or them together to get a composite function
B. The cool part about truth tables:
The interesting thing about truth tables is that we can
use them as guide lines on how to write SOP equations.
EX:
Inputs Output
A B C O
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Output = /A*/B*/C + /A*B*/C+/A*B*C+A*B*/C+A*B*C
As Gates:
See Diagram
Note that I've used "multi-input" gates.
We can construct these gates from even simpler gates:
See Diagram
(Although in CMOS this isn't nesc.)
What this REALLY means to US -
Any logical operation which we can write as a table,
we can convert into SOP equations and hence into gates
and a real machine! (THIS IS VERY IMPORTANT!!!)
The basic process:
Find every "one" output.
"Sum" a product term that "selects" that row
(I.e. an equation term that will only be "true"
for those inputs)
ANYTHING that we can describe with a binary table
we can build a digital machine to do!!!
(This is absolutely KEY!)
C. Bigger Parts:
Often in computers we are really worried about the movement
and manipulation of information, so we develop "bigger"
parts so we can concentrate on this.
We'll develop parts two ways:
1. Functional - A purely mechanical technique
a. Start with tables to describe operation
b. Convert to SOP equation (1 row at a time)
c. Write out function
2. Conceptual - We know what concept we want in the
end, so we'll try to build it out of smaller parts.
By the end of this course we should understand how the ALU
and registers work: (As well as a general idea of the control)
See Diagram
Why?
1. Verify that programs (algorithms) can be converted to ASM
Understand efficency
Understanding of how instructions & memory function to help
debug problems at the higher level:
Ex: Stack Overwrite changing a variable....
2. Better understanding of how to use the machine and higher level lang.
appropriately/efficiently
So, let's construct some of these parts and write them out
as logic equations/gates.
1. Multiplexor (MUX) - Many-to-one device (Like a printer selector)
Inputs: I0, I1, I2, ... S0, S1, S2
Outputs: 0
Concept: We'll start simple, but the idea is to use the
RS field to select an input to the ALU
The S bits are "selector" lines that select which input
should be "copied" through to the output.
Symbols: See Diagram
Ex: 2-bit MUX
Table:
Inputs Output
I0 I1 S O
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
O=/I0*I1*S+I0*/I1*/S+I0*I1*/S+I1*I0*S
Or we could "think" about it: 0=I0*/S+I1*S
4-bit multiplexor:
4 inputs, 2 selector lines, 1 output.
The multiplexor is the magic selector that we'll be using
quite often to control where information comes from in our
simple ALU.
2. Decoder - Takes an N-input binary number and converts
it to a single of 2^N outputs.
Often this is used "decode" instructions and to select
(via a MUX) the appropriate part of the CPU for a specific
op-code. (Often all possible functions are performed, but
only one is "selected" (via the op-code) as the correct
one to put back in a register.
Ex: 2-to-4 Decoder
2 inputs, 4 outputs
I0 I1 O0 O1 O2 O3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
3. Simple "Selector"
I want a device that will Recognize ONLY:
the J instruction:
op=2
Out = /I(31)*/I(30)*/I(29)*/I(28)*I(27)*/I(26)
D. Two Level Logic
Any Truth table can be created using only two levels of logic.
(Only AND and OR gates need be used, but each level must allow
for multiple inputs)
History: Hardware designers early on realized that it's very difficult
and costly to build "unique" circuits for each new project
out of simple elements. Companies saw a demand for
"programmable" parts - parts that could implement a LOT of
different simple logic equations.
These parts are typically OTP (One time programmable)
A hardware designer focuses on the equations that they
should implement. Then they put the chip into a programmer
which "burns" the equations into the chip via a programmable
interconnect matrix.
Simple Equation for a 2-input MUX:
Out = /S*I0 + S*I1
PLA - Programmable ANDs and Programmable ORs
The ultimate in programmability
A lot of space is used for the interconnect array(s)
Slower - longer wires
PAL - Programmable AND, fixed ORs
Smaller Interconnect arrays, but still quite flexible
ROM - Fixed AND connected to programmable OR
N-Inputs each AND uniquely "selects" one of the 2^N
possible input patterns.
GREAT for lookup tables - I.e. Memory (Read Only Memory)
E. NAND Gate - A "logically complete" gate
All other gates can be built from the NAND gate,
so we call it logically complete:
A B A NAND B
0 0 1
0 1 1
1 0 1
1 1 0
NOT A = A NAND 1
We can Create NOTs from NANDs and build an AND
Or ORs or NORs, etc.
Intro to Timing Diagrams - The OR from NAND
III. Next Time:
A. Continue with Logic / Machines
B. Return Test #2 & "Makeup" problem:
Problem 8, worth 8 points.
MUST use all stack / reg conventions and
have a very clear diagram of stack usage.