I. Last Time:
   Lab #3 Demos!!!
   Hw #6 DUE!!!
   Lab #4 Posted Today (~ length of lab #2+)

   If grade <60%, will be dropped today!

   A. Lab #4 Discussion!

   B. Truth Tables & Gates:
      We can build any machine we can describe in binary!
      Functional Approach:
          1. Build Binary table
              Inputs and Outputs
          2. Find SOP equations:
               For each output
                   For each '1' 
                       Create a Product of inputs
                   sum them
          3. Draw a diagram
 
   C. Simple Machines:
      MUX
      Decoder

II. New Stuff
    A. Two Level Logic
       Any Truth table can be created using only two levels of logic.
       (Only AND and OR gates need be used, but each level must allow
        for multiple inputs)
       History: Hardware designers early on realized that it's very difficult
                and costly to build "unique" circuits for each new project 
                out of simple elements. Companies saw a demand for 
                "programmable" parts - parts that could implement a LOT of
                different simple logic equations. 
                These parts are typically OTP (One time programmable)
                A hardware designer focuses on the equations that they
                should implement. Then they put the chip into a programmer
                which "burns" the equations into the chip via a programmable
                interconnect matrix.

       Simple Equation for a 2-input MUX:
           Out = /S*I0 + S*I1

       PLA - Programmable ANDs and Programmable ORs
             The ultimate in programmability
             A lot of space is used for the interconnect array(s)
             Slower - longer wires

       PAL - Programmable AND, fixed ORs
             Smaller Interconnect arrays, but still quite flexible
               
       ROM - Fixed AND connected to programmable OR
             N-Inputs each AND uniquely "selects" one of the 2^N
               possible input patterns.
             GREAT for lookup tables - I.e. Memory (Read Only Memory)

    B. NAND Gate - A "logically complete" gate
       All other gates can be built from the NAND gate, 
       so we call it logically complete:
         A B   A NAND B 
         0 0       1
         0 1       1
         1 0       1
         1 1       0
       NOT A = A NAND 1
       We can Create NOTs from NANDs and build an AND
       Or ORs or NORs, etc.

    C. Timing: We'll have to "wait" for adds to complete
       This is propagation delay that is inherent in many 
       math units - this is why when optimizing, compilers 
       often avoid math operations - they are typically slower.
       (Multiplication is repeated addition, so it's worse)

    D. Subtraction: How can we accomplish subtraction?
       Opcode: Sub 11
       Subtraction was just 2's compliment (i.e. negate the number)
       and Add it...(This is one reason we use 2's compliment 
       the adding and subtraction process are virtually identical)
       How do we do 2's compliment:
          Right most one, and flip everything to it's left...
          OR Invert everything and add one
             Ex: 01101
             Ex: 00100
       ALU Modifications: 
          Use and "invert mux" to determine whether to invert or not.
          Put the 1 in the carry in
       How do we decide when to do these? Use an opcode bit.

     E. Unsigned vs. Signed arithmatic
        What's the real difference?
        The process of each is the same - what differs is overflow!
        Let's build an overflow detector
        (This will be fed into the exception unit of the CPU)
        Unsigned: 
           Ex: 01+01 = 10 (Fine)
               11+01 = 100 (Overflow)
           Let's take a look at this on the numberline.
           Carryout means we have overflow - i.e. our number doesn't fit
           in the space we have provided!

        Signed: 00 (0) 01 (1) 10 (-2) 11 (-1)
              00+01 = 01
              00+11 = 11
              01+11 = 100 = 00
              11+11 = 110 = 10
              10+10 = 100 = 00 (Opps!)
           Let's take a look at this on the numberline.
              1) A pos + neg = No Problem
              2) A neg + neg = Potential problem 
              3) A pos + pos = potential problem
           What indicates a problem is when we add 2 numbers of
           the same sign and get a different sign. 
           (Remember the upper most bit is the "sign bit")
        
        Opcodes:
            Addu 110, Subu 111 
         
        Overflow = Unsigned*CarryOut + 
                   Signed*A(high)*B(high)*/C(high) +
                   Signed*/A(high)*/B(high)*C(high)

     F. Let's add a few more instructions to our CPU
        SLT Opcode 100

        NOT A Opcode 101

III. Next Time:
     A. Continue with Logic / Machines
     B. Return Test #2 & "Makeup" problem:
        Problem 8, worth 8 points.
        MUST use all stack / reg conventions and 
        have a very clear diagram of stack usage.