I. Last Time:
   Lab #3 Demos!!!
   Lab #4 Posted!!! (~ length of lab #2+)

   A. Lab #4 Discussion!
      print_board return value...
      Check List posted
      Corrected Sample Run posted.

   B. Two Level Logic
       PLA - Programmable ANDs and Programmable ORs
             The ultimate in programmability
             A lot of space is used for the interconnect array(s)
             Slower - longer wires

       PAL - Programmable AND, fixed ORs
             Smaller Interconnect arrays, but still quite flexible
               
       ROM - Fixed AND connected to programmable OR
             N-Inputs each AND uniquely "selects" one of the 2^N
               possible input patterns.
             GREAT for lookup tables - I.e. Memory (Read Only Memory)

       These all are ideally designed for SOP equations.
       (Generally we just write the equations and use a piece 
        of software (similiar to a compiler) to actually
        figure out the fuses & program it.)

II. New Stuff
    A. NAND Gate - A "logically complete" gate
       All other gates can be built from the NAND gate, 
       so we call it logically complete:
         A B   A NAND B 
         0 0       1
         0 1       1
         1 0       1
         1 1       0
       NOT A = A NAND 1
       We can Create NOTs from NANDs and build an AND
       Or ORs or NORs, etc.

    B. Let's Build an ALU!
       We want to build a 1-bit computer. 
       We'll start with functional building blocks to 
       try to make it easier to understand (than just logic eqns)

       ALU: 
          Operations: AND, OR, and ADD
          Op-Codes: 00, 01, 10 (in binary)
          Will take 2 inputs and produce a single output

          We'll create a new part (a multiplexor) for selecting 
          the output based on the input.

       What about a 2 bit ALU? Can We Extend these "Bit Cells?"
          For Everything but Add, it seems to work.

       The Full Adder: Carry in and Carry Out
          If the Adder utilizes a carry in and a carry out, 
          we'll be o.k.

       What about Subtraction? How did we do this earlier?
       2's compliment - Remember inverting and adding 1?

       What about Mult/Div - They'll come later.

    C. Timing: We'll have to "wait" for adds to complete
       This is propagation delay that is inherent in many 
       math units - this is why when optimizing, compilers 
       often avoid math operations - they are typically slower.
       (Multiplication is repeated addition, so it's worse)

    D. Subtraction: How can we accomplish subtraction?
       Opcode: Sub 11
       Subtraction was just 2's compliment (i.e. negate the number)
       and Add it...(This is one reason we use 2's compliment 
       the adding and subtraction process are virtually identical)
       How do we do 2's compliment:
          Right most one, and flip everything to it's left...
          OR Invert everything and add one
             Ex: 01101
             Ex: 00100
       ALU Modifications: 
          Use and "invert mux" to determine whether to invert or not.
          Put the 1 in the carry in
       How do we decide when to do these? Use an opcode bit.

     E. Unsigned vs. Signed arithmatic
        What's the real difference?
        The process of each is the same - what differs is overflow!
        Let's build an overflow detector
        (This will be fed into the exception unit of the CPU)
        Unsigned: 
           Ex: 01+01 = 10 (Fine)
               11+01 = 100 (Overflow)
           Let's take a look at this on the numberline.
           Carryout means we have overflow - i.e. our number doesn't fit
           in the space we have provided!

        Signed: 00 (0) 01 (1) 10 (-2) 11 (-1)
              00+01 = 01
              00+11 = 11
              01+11 = 100 = 00
              11+11 = 110 = 10
              10+10 = 100 = 00 (Opps!)
           Let's take a look at this on the numberline.
              1) A pos + neg = No Problem
              2) A neg + neg = Potential problem 
              3) A pos + pos = potential problem
           What indicates a problem is when we add 2 numbers of
           the same sign and get a different sign. 
           (Remember the upper most bit is the "sign bit")
        
        Opcodes:
            Addu 110, Subu 111 
         
        Overflow = Unsigned*CarryOut + 
                   Signed*A(high)*B(high)*/C(high) +
                   Signed*/A(high)*/B(high)*C(high)

     F. Let's add a few more instructions to our CPU
        SLT Opcode 100

        NOT A Opcode 101

     G. MIPS & Logic Instructions:
        MIPS logic instructions are BITWISE Logic: 
          and/andi = bitwise and (diagram) = & in C
          or/ori = bitwise or = | in C
          not = bitwise not = ~ in C
          sll = Shifting Left Logical Constant
          sllv = Shifting Left Logical Variable
          srl = Shifting Right Logical Constant
          sra = Shift Right Arithmetic
          srlv = Shift Right logical variable
          srav = Shift right arithmetic variable
          xor/xori
          nor

     H. Weird Stuff - The RS-Latch!
       Latches & Registers: bit memory elements:
       1. NOR Gate
          A  B   A NOR B
          0  0      1
          0  1      0
          1  0      0
          1  1      0
         Note: A 1 input = a 0 output

       2. Cross Coupled NOR - How's this beast work?
          Timing Diagram
          (This is an RS Latch - Good for a burgler alarm
           because it "Latches" when set)

       3. The Race Condition

     I. The Solution to Racing: Clocking 
        (Build a circuit to prevent race conditions)
         The D-Latch (D for Data, Latch for "latching onto" the data)

     J. Even More percise timing - the D Flip-Flop 
        (The Value Flips one Way, then Flops back the other)
        The Beauty of the flip flop is that we "capture" 
        information at very precise time intervals

III. Next Time:
     A. Continue with multi-bit ALUs
     B. Begin Memory Cells