I. Last Time:
   Lab #4 Posted!!! (~ length of lab #2+)

   A. Lab #4 Discussion!
      Questions?
      Development Techniques?
      Testing individual functions?

   B. NAND Gate - Logically Complete
      (IF the EE's can build it, we can build nearly any machine)

   C. Simple ALU:
         Op Code Selects the Function via Multiplexor
         Individual components "compute" the function
       Half Adder:
          Half the adding process (Adds 2 digits)
       Full Adder:
          The Entire Adding process (2 digits+carry)

       Subtraction: We just add a negative!
          Invert and Add 1 To Subtract

II. New Stuff
    A. Let's Build an ALU - Continued!
       ALU: 
          Operations: AND, OR, and ADD
          Op-Codes: 00, 01, 10 (in binary)
          Will take 2 inputs and produce a single output

       What about Mult/Div - They'll come later.
       (Although Mult can be just repeated addition)

    B. Timing: We'll have to "wait" for adds to complete
       This is propagation delay that is inherent in many 
       math units - this is why when optimizing, compilers 
       often avoid math operations - they are typically slower.
       (Multiplication is repeated addition, so it's worse)

    C. Unsigned vs. Signed arithmatic
        What's the real difference?
        The process of each is the same - what differs is overflow!
        Let's build an overflow detector
        (This will be fed into the exception unit of the CPU)
        Unsigned: 
           Ex: 01+01 = 10 (Fine)
               11+01 = 100 (Overflow)
           Let's take a look at this on the numberline.
           Carryout means we have overflow - i.e. our number doesn't fit
           in the space we have provided!

        Signed: 00 (0) 01 (1) 10 (-2) 11 (-1)
              00+01 = 01
              00+11 = 11
              01+11 = 100 = 00
              11+11 = 110 = 10
              10+10 = 100 = 00 (Opps!)
           Let's take a look at this on the numberline.
              1) A pos + neg = No Problem
              2) A neg + neg = Potential problem 
              3) A pos + pos = potential problem
           What indicates a problem is when we add 2 numbers of
           the same sign and get a different sign. 
           (Remember the upper most bit is the "sign bit")
        
        Opcodes:
            Addu 110, Subu 111 
         
        Overflow = Unsigned*CarryOut + 
                   Signed*A(high)*B(high)*/C(high) +
                   Signed*/A(high)*/B(high)*C(high)

     D. Let's add a few more instructions to our CPU
        SLT Opcode 100

        NOT A Opcode 101

     E. MIPS & Logic Instructions:
        MIPS logic instructions are BITWISE Logic: 
          and/andi = bitwise and (diagram) = & in C
          or/ori = bitwise or = | in C
          not = bitwise not = ~ in C
          sll = Shifting Left Logical Constant
          sllv = Shifting Left Logical Variable
          srl = Shifting Right Logical Constant
          sra = Shift Right Arithmetic
          srlv = Shift Right logical variable
          srav = Shift right arithmetic variable
          xor/xori
          nor

     F. Weird Stuff - The RS-Latch!
       Latches & Registers: bit memory elements:
       1. NOR Gate
          A  B   A NOR B
          0  0      1
          0  1      0
          1  0      0
          1  1      0
         Note: A 1 input = a 0 output

       2. Cross Coupled NOR - How's this beast work?
          Timing Diagram
          (This is an RS Latch - Good for a burgler alarm
           because it "Latches" when set)

       3. The Race Condition

     I. The Solution to Racing: Clocking 
        (Build a circuit to prevent race conditions)
         The D-Latch (D for Data, Latch for "latching onto" the data)

     J. Even More percise timing - the D Flip-Flop 
        (The Value Flips one Way, then Flops back the other)
        The Beauty of the flip flop is that we "capture" 
        information at very precise time intervals

III. Next Time:
     C. Begin/Continue Memory Cells