I. Last Time:
    A. Timing: We'll have to "wait" for adds to complete
       This is propagation delay that is inherent in many 
       math units - this is why when optimizing, compilers 
       often avoid math operations - they are typically slower.
       (Multiplication is repeated addition, so it's worse)

    B. Subtraction: How can we accomplish subtraction?
       Opcode: Sub 11
       Subtraction was just 2's compliment (i.e. negate the number)
       and Add it...(This is one reason we use 2's compliment 
       the adding and subtraction process are virtually identical)
       How do we do 2's compliment:
          Right most one, and flip everything to it's left...
          OR Invert everything and add one
             Ex: 01101
             Ex: 00100
          A-B = A+(-B) = A+(negate B+1) = A+(negate B)+1 
       ALU Modifications: 
          Use and "invert mux" to determine whether to invert or not.
          Put the 1 in the carry in
       How do we decide when to do these? Use an opcode bit.
II. New Stuff:           
    A. Unsigned vs. Signed arithmatic
       What's the real difference?
       The process of each is the same - what differs is overflow!
       Let's build an overflow detector
       (This will be fed into the exception unit of the CPU)
       Unsigned: 
          Ex: 01+01 = 10 (Fine)
              11+01 = 100 (Overflow)
          Let's take a look at this on the numberline.
          Carryout means we have overflow - i.e. our number doesn't fit
          in the space we have provided!

       Signed: 00 (0) 01 (1) 10 (-2) 11 (-1)
             00+01 = 01
             00+11 = 11
             01+11 = 100 = 00
             11+11 = 110 = 10
             10+10 = 100 = 00 (Opps!)
          Let's take a look at this on the numberline.
             1) A pos + neg = No Problem
             2) A neg + neg = Potential problem 
             3) A pos + pos = potential problem
          What indicates a problem is when we add 2 numbers of
          the same sign and get a different sign. 
          (Remember the upper most bit is the "sign bit")
        
       Opcodes:
           Addu 110, Subu 111 
        
        Overflow = Unsigned*CarryOut + 
                   Signed*A(high)*B(high)*/C(high) +
                   Signed*/A(high)*/B(high)*C(high)

    B. Let's add a few more instructions to our CPU
       SLT Opcode 100
       How do we check?
       Subtract - if result is neg, than A was lt B
           Overflow problem...
           If A is neg and OF, than A is less
       NOT A Opcode 101
       BEQ Support (Differs from book)
          if A*B+/A*/B in each bit cell. 
              All Anded together
          Faster than sub check 0

    C. Latches & Registers: bit memory elements:
       1. NOR Gate
          A  B   A NOR B
          0  0      1
          0  1      0
          1  0      0
          1  1      0
       2. Cross Coupled NOR - How's this beast work
          Timing Diagram
          (This is an RS Latch - Good for a burgler alarm
           because it "Latches" when set)
       3. The Race Condition
            
III. Next Time:
     A. MIPS Logic instructions
     B. Building Blocks of Memory and registers continued
     B. Registers
     C. Memory
     D. Simple CPU overview
     E. Multiply & Divide
     F. The State Machine