WIMP51: Weekend Instructional Microprocessor

Goals: To create the WIMP51 processor in Quartus II Digital Circuit Design software, using Block Diagram Files (BDF), which can be downloaded on the Altera® DE2 FPGA board for experimentation. The implementation aims to:

· Provide a visualization tool, using BDF, which allows a user to see how the different sub-systems are connected with each other.

· Provide an interactive hardware facility, on the FPGA board, to view the different control signals and internal register data, during the FETCH, DECODE and EXECUTE cycle of each instruction, as the processor sequences through the entered program.

· Provide a development platform, for students, to create their own WIMP51 version by adding additional instruction/s to the included instruction set.

Creators:

· Larry Garringer

· Mason Marshall

· Ariel Moss

· Dr. Rohit Dua: Advisor

Inspiration: The WIMP51 processor was originally created by D. Sullins, H. Pottinger and D. G. Beetner [1-2]. Salient features of the implementation were:

· The processor was implemented using synthesizable VHDL.

· An interactive graphical simulator was also created to be used in lab [1-2].

In addition to the two software/hardware based experiments proposed by [1-2], a third experiment, which effectively became the first project in the Digital Systems Design course, was suggested and created by [1-2].

Motivation behind a similar but different implementation:

· Students taking the prerequisite course, Introduction to Computer Engineering, are only briefly exposed to VHDL programming. Most of the experimentation and hardware development, in lecture and laboratory, is performed, in Quartus II software, using BDF, and then downloaded on the Altera® FPGA board for testing. Creating the WIMP51 processor using BDFs, may give students a better visualization tool into the internal connections of the different sub-systems.

· Since students, taking this course, are already experienced in using Quartus II software and the Altera® FPGA board, it may be relatively easy to implement the project, which includes modifying and enhancing the WIMP51 processor and its instruction set.

A Similar but Different Implementation: The sources of current implementation were:

· The architecture [1-2]:

NOTE: The current implementation does not include the PSEN signal.

· The instruction set [1-2]:

NOTE: The instruction set was modified, for ease of implementation, for the last two instructions (JZ and SJMP). The new instruction set is

Interactive WIMP51 circuit diagram: WORKS BEST IN INTERNET EXPLORER!

Note: Clicking on the above link will open the top level diagram of the WIMP51 processor. Zoom in to view the interconnections. As you zoom in, you will find clickable links (Text in Gray Boxes), which will take you to lower level BDF.

Sample Videos: Click on the images below to access videos, which show the salient features of the current WIMP51 implementation through 3 sample programs.

WIMP51 Write Program Introduction

WIMP51 Program Upload Demonstration

WIMP51 Main Program Introduction

WIMP51 Program 1 Demonstration

WIMP51 Program 2 Demonstration

WIMP51 Program 3 Demonstration

References:

[1] D. Sullins, H. Pottinger, and D. G. Beetner, “The WIMP51: A Simple Processor and Visualization Tool to Introduce Undergraduates to Computer Organization,” Computers in Education Journal, vol. 13, pp 17-23, Jan. 2003.

[2] D. Sullins, H. Pottinger, D. Beetner, "The WIMP51: A Simple Processor and Visualization Tool to Introduce Undergraduates to Computer Organization," ASEE, 2002, p 2232. (Refereed paper).

Design Team: Mason Marshall (left), Dr. Rohit Dua (Advisor, center), Ariel Moss (right), & Larry Garringer