Hardware-Software Co-Simulation

The following clip shows the process of simulating the 8051 with an external 32k code space using the Xess XS40 prototype board. The windows, starting with the upper right corner are: code file in Intel Hex format (hello.hex), source code for a VHDL model of 32k static ram, trace window showing a portion of the 8051 startup sequence, and schematic window showing a portion of the XS40 schematic.

As the simulation progresses, the code byte being executed is highlighted in the code file.

The 32k static ram model is a modified version of a public domain sram model. It was modified locally to read Intel hex format object code files produced by the Keil 8051 Microcontroller Development Tools. The nvsram model contains a parameter called download_filename which can be set to point to a hex object code file.  This file is executed by the 8051 simulation model.

The trace window shows a timing diagram of the 8051 during program execution.

The schematic window shows the schematic designed by the student. The top level schematic shows the XS40's 8051, 32k sram, and a Xilinx 4k FPGA (field programmable gate array), though only a portion is shown in this animation. Students complete their hardware design under the FPGA symbol and attach a code file to the sram model. The result is a complete hardware-software prototype using the XS40 board.  This prototype may be thoroughly tested using the proposed 8051 simulation model.

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Document maintained by daryl@ece.umr.edu
Last Modified 15-Feb-1999